This invention relates generally to microwave transistor packages and method of manufacturing such packages and more particularly microwave transistor packages having low parasitic reactance and adapted to have packaged therein impedance matching circuitry for the packaged transistor.
As is known in the art, in order to provide transistor components having relatively high power, high efficiency and high gain, in many applications it is necessary to connect in parallel a large number of individual transistor cells within a hermetically sealed package. Increasing the number of cells in parallel, however. reduces the input impedance of the transistor component. For example, a typical unmatched 30 watt bi-polar transistor component having parallel connected cells at L-band has an input impedance of about 0.3 ohms, while the input impedance of a typical 100 watt component is typically less than 0.1 ohms. This relatively low impedance is clearly very difficult to impedance match to, and reproducibility suffers as the impedance to be matched becomes sensitive to component variations and manufacturing or assembly tolerances. Thus, it becomes highly desirable to provide an impedance matching network within the package, since if the matching network were outside the package relatively long lead wires would be required thereby increasing the inductive reactance which must be cancelled by the matching network.
As is also known in the art, a typical microwave transistor package includes a beryllia insulator to provide a low thermal resistance from the transistor die to the package heat sink base or header. The upper and lower surfaces of the beryllia insulator have gold layers for attachment to the transistor die on the upper surface and for attachment to the header on the lower surface. The header also serves as the ground plane conductor. The transistor typically has its collector contact formed on the bottom of the die and hence, in those configurations, requiring a grounded, or common base configuration, it is necessary to electrically connect the base electrode, formed on the upper surface of the transistor die, to the header. This connector is typically done with a wire lead and it is generally desirable to use relatively short leads in order to reduce the inductive reactance of such wire lead since such reactance becomes part of the input impedance to the transistor component. One technique suggested to reduce the length of the lead and hence reduce its parasitic inductive reactance is to position the beryllia between a pair of conductive rails, as discussed in U.S. Pat. No. 3,784,884, issued Jan. 8, 1974, Demir S. Zoroglu, inventor. As discussed in such patent, bonding wires are used to connect the transistor to the grounded rails and the length of such wires is reduced by having the height of the grounded bonding rails approximately equal to the thickness of the beryllia insulator so that the bonding surface of the rail is almost even with the transistor die. However, as described in U.S. Pat. No. 4,150,393, issued Apr. 17, 1979, Richard W. Wilson and Marcy B. Goldstein, inventors, and assigned to the same assignee as U.S. Pat. No. 3,784,884, referred to above, relatively expensive coined bonding rails are required in such package.
One technique suggested to remove the requirement for the coined bonding rails discussed in U.S. Pat. No. 4,784,884, referred to above, is to provide a copper header with a pedestal having a channel formed in the upper surface thereof into which the metallized beryllium insulator is positioned as discussed in U.S. Pat. No. 4,150,393, referred to above. Also included in the package discussed in the latter patent is a toroid shaped alumina ceramic insulator which encircles the sides of the pedestal portion of the header and which has lower surfaces which rest on the lower base portion of the header. The upper surface of the insulator support metallized conductive leads to the package. The alumina insulator, conductive coated beryllia insulator and metal conductive leads are brazed together in one operation to form a single unit. It is first noted, however, that, as mentioned above, in high power devices the impedance matching network should be included within the package and with the relatively small package described above, while patentee suggests that surfaces of the pedestal can be utilized to have a MOS chip capacitor attached to it, if the size of the pedestal were increased to have sufficient surface area to accomodate impedance matching devices the toroid shaped ceramic insulator would tend to splinter during brazing of the ceramic insulator to the header, since mechanical stresses during brazing cause the insulator to splinter because of the great difference between the relatively low coefficient of thermal expansion of the ceramic insulator and the relatively high thermal coefficient of expansion of the copper header. However, the cylindrical form of the package does not allow it to be readily used with more readily available circuitry which is designed to receive rectangular packages. Further, increasing the size of the pedestal header to accomplish the impedance matching devices tends to agravate the effect of the great difference between the thermal expansion properties of the header and the ceramic on the ceramic's tendency to splinter.